Infineon /XMC4200 /VADC_G0 /RCR[0]

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCR[0]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DRCTR0 (value1)DMM0 (value1)WFR 0 (value1)FEN0 (value1)SRGEN

FEN=value1, SRGEN=value1, WFR=value1, DMM=value1

Description

Result Control Register

Fields

DRCTR

Data Reduction Control

DMM

Data Modification Mode

0 (value1): Standard data reduction (accumulation)

1 (value2): Result filtering mode

2 (value3): Difference mode

WFR

Wait-for-Read Mode Enable

0 (value1): Overwrite mode

1 (value2): Wait-for-read mode enabled for this register

FEN

FIFO Mode Enable

0 (value1): Separate result register

1 (value2): Part of a FIFO structure: copy each new valid result

SRGEN

Service Request Generation Enable

0 (value1): No service request

1 (value2): Service request after a result event

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